Method And Apparatus For Register Renaming Using Multiple Physical Register Files And Avoiding Associative Search

ABSTRACT

A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions from one or more threads, the method comprising: using a DEF table to store the instruction dependencies between the plurality of instructions using the instruction tags, the DEF table being indexed by a logical register name and including one entry per logical register; using a rename USE table indexed by the instruction tags to store logical-to-physical register mapping information shared by multiple sets of different types of non-architected copies of logical registers used by multiple threads; using a last USE table to transfer data of the multiple sets of different types of non-architected copies of logical registers into the first set of architected registered files, the last USE table being indexed by a physical register name in the second set of rename registered files; and performing the register renaming scheme at the instruction dispatch or wake-up/issue time.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/456,878 filed Jul. 12, 2006, the contents of which are incorporatedby reference herein in their entirety.

TRADEMARKS

IBM® is a registered trademark of International Business MachinesCorporation, Armonk, N.Y., U.S.A. Other names used herein may beregistered trademarks, trademarks or product names of InternationalBusiness Machines Corporation or other companies.

GOVERNMENT INTEREST

This invention was made with Government support under contract No.:NBCH3039004 awarded by Defense Advanced Research Projects Agency(DARPA). The Government has certain rights in this invention.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to digital data processing systems, andparticularly to a renaming scheme used for supporting out-of-orderspeculative execution of instructions.

2. Description of Background

There are many factors that affect performance and effective utilizationof resources in modern processors. Some of these factors include datadependencies between instructions as specified by semantics of aprogram, a finite number of architected registers determined by aninstruction set architecture (ISA), and an inability to disambiguate allmemory references at compile time by limiting an amount ofinstruction-level parallelism (ILP) that is exposed through programbinaries.

Several micro-architecture techniques are used in the processors toextract more ILP from programs. For example, a small number ofarchitected or logical register names causes output andanti-dependencies between instructions in a program binary. These falsedependencies affect processor performance because it forces serializedexecution of instructions. Register renaming is a technique used by aninstruction-scheduling unit of out-of-order superscalar processors toeliminate serialized execution of instructions due to output andanti-dependencies. Register renaming is a process of mapping arelatively small architected or logical register name space to a largephysical register name space in order to enable out-of-order executionof multiple instructions in such a manner that they are only constrainedby true data dependencies. Moreover, the register renaming logic withthe help of some additional hardware is also used to enable speculativeexecution of instructions via maintaining multiple versions of logicalregisters (in different physical registers) and providing support torestore the processor state to an appropriate non-speculative statewhenever the speculative execution turns out to be wrong.

Several hardware techniques have been proposed and used for implementingregister renaming for out-of-order execution of instructions. Theseregister-renaming techniques are broadly classified into two approaches.One approach is based on Tomalosulo's algorithm using reservationstations and the other approach is based on a mapping table. Additionalstructures such as reorder buffers, history buffers, future files,checkpoint/backup register files or shadow mapping tables may be addedor combined with the basic renaming hardware to save and restore thearchitected register state for supporting speculative execution andprecise interrupts.

In particular, the instructions in a program binary use a small set oflogical (or architected) register names specified by the instruction setarchitecture (ISA) of the processor. The logical registers are mapped toa larger set of physical registers by the register renaming hardware.The physical registers used for storing the logical register values areorganized as a single register file or two register files, those beingan Architected Register File (ARF) and Rename Register File (RRF).

The register contents are copied from rename register file toarchitected register file (and marked free for renaming) whenever allthe instructions referring to a particular architected register arecompleted. Note that, unlike in a compiler, the only way to know the endof a live range is whenever it becomes the target of a younginstruction. However, in our renaming scheme, for the purpose of copyinga rename register entry, it is assumed that a live range of anarchitected register ends whenever none of the in-flight instructionsuse it as a source register. To identify the set of “active” registersthat will not be read by any in-flight instructions, a counter may beassociated with each mapper table entry as described in the conferencepaper entitled “Register Renaming and Dynamic Speculation: anAlternative Approach” by Moudgill et al. published in the Proceedings ofthe 26th annual international symposium on Microarchitecture, 1993. Thecounter associated with a renamed physical register may be incrementedat dispatch of every source register mapped to it and decrementedwhenever such an instruction completes. This counter-based physicalregister solution is an expensive solution that is not desirable. Theexemplary embodiments propose detecting the end of “live-range” amongthe instructions in flight in order to reclaim a physical register inRRF used for renaming.

One of the common characteristics of all the prior register renamingschemes is that all of them use an associative search by using eitherCAM (Content Accessible Memory) structures or an array of parallelcomparators on tables with large number of entries. The complexity andpower consumed by the logic structures used for implementing suchassociative search functions is one of the major inhibitors forimplementing high frequency out-of-order superscalar processors.Therefore a register-renaming scheme that does not involve anyassociative search functions is highly desirable.

In particular, it has been shown that out-of-order execution would helpimprove performance of a program, in particular SPEC INT benchmarks.However, having a separate mapper (register renaming unit) for each typeof registers is expensive, making it unattractive for wide-issuehigh-frequency superscalar processor designs. The exemplary embodimentsuse processor architectures with a separate set of architected registerfiles for each type of registers and threads along with a small set ofphysical registers using a shared mapper for renaming. As evident fromthe above discussion, conventional methods have limitations orinefficiencies, requiring a different approach to efficiently manage therenaming operations in an out-of-order superscalar processor.

Thus, it is well known that renaming registers affects effectiveutilization of resources in modern processors. Therefore, it is desiredto develop an efficient method and apparatus for renaming registers thatreduces hardware complexity as well as the number of rename registers byusing multiple physical register files and avoiding associativesearching.

SUMMARY OF THE INVENTION

The shortcomings of the prior art are overcome and additional advantagesare provided through the provision of a method for implementing aregister renaming scheme for a digital data processor using a pluralityof physical register files for supporting out-of-order execution of aplurality of instructions, the method comprising: partitioning theplurality of physical register files into a first set of register fileshaving a fixed one-to-one mapping with a first set of logical registersin the architected state and into a second set of register files beingmapped to a second set having multiple copies of logical registers in anon-architected state by a register-renaming unit; assigning aninstruction tag to each of the plurality of instructions for trackinginstruction dependencies; using a DEF table to store the instructiondependencies between the plurality of instructions using the instructiontags, the DEF table being indexed by a logical register name andincluding one entry per logical register; using a rename USE tableindexed by the instruction tags to store logical-to-physical registermapping information shared by multiple sets of different types ofnon-architected copies of logical registers used by multiple threads;using a last USE table to transfer data of the multiple sets ofdifferent types of non-architected copies of logical registers into thefirst set of architected registered files, the last USE table beingindexed by a physical register name in the second set of renameregistered files; and performing the register renaming scheme at theinstruction dispatch or wake-up/issue time in order to reduce a numberof the plurality of physical register files.

The shortcomings of the prior art are overcome and additional advantagesare provided through the provision of a system for implementing aregister renaming scheme for a digital data processor using a pluralityof physical register files for supporting out-of-order execution of aplurality of instructions, the system comprising: a network; and a hostsystem in communication with the network, the host system includingsoftware to implement a method comprising: partitioning the plurality ofphysical register files into a first set of register files having afixed one-to-one mapping with a first set of logical registers in thearchitected state and into a second set of register files being mappedto a second set having multiple copies of logical registers in anon-architected state by a register-renaming unit; assigning aninstruction tag to each of the plurality of instructions for trackinginstruction dependencies; using a DEF table to store the instructiondependencies between the plurality of instructions using the instructiontags, the DEF table being indexed by a logical register name andincluding one entry per logical register; using a rename USE tableindexed by the instruction tags to store logical-to-physical registermapping information shared by multiple sets of different types ofnon-architected copies of logical registers used by multiple threads;using a last USE table to transfer data of the multiple sets ofdifferent types of non-architected copies of logical registers into thefirst set of architected registered files, the last USE table beingindexed by a physical register name in the second set of renameregistered files; and performing the register renaming scheme at aninstruction dispatch or wake-up/issue time in order to reduce a numberof the plurality of physical register files.

Additional features and advantages are realized through the techniquesof the present invention. Other embodiments and aspects of the inventionare described in detail herein and are considered a part of the claimedinvention. For a better understanding of the invention with advantagesand features, refer to the description and the drawings.

TECHNICAL EFFECTS

As a result of the summarized invention, technically we have achieved asolution that provides for an efficient register-renaming scheme byusing multiple physical register files and avoiding associativesearching.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter, which is regarded as the invention, is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The foregoing and other objects, features, andadvantages of the invention are apparent from the following detaileddescription taken in conjunction with the accompanying drawings inwhich:

FIG. 1 illustrates one example of a pipeline block diagram of aprocessor for register renaming and speculative out-of-order executionusing two sets of physical register files in accordance with exemplaryembodiments of the present invention;

FIG. 2 illustrates one example of a Last Use table; and

FIG. 3 illustrates one example of a structure for assigning physicalregisters to logical registers and reclaiming rename registers accordingto the exemplary embodiments of the present invention;

FIG. 4 illustrates one example of a table showing operations forallocating and freeing physical registers to logical registers inaccordance with the exemplary embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

One aspect of the exemplary embodiments is a method for renamingregisters. Another aspect of the exemplary embodiments is a method forreducing the complexity and size of register renaming hardware by usinga shared mapping table indexed by instruction tags to storelogical-to-physical register mapping for different types of logicalregisters (such as general-purpose or integer registers (GPRs),floating-point registers (FPRs), vector registers (VRs), etc.) used bymultiple threads and avoiding associative searching.

The exemplary embodiments provide for a technique for implementing anarea and power efficient renaming scheme for a digital data processorusing multiple physical register files. The exemplary embodimentsfurther provide for an improved pipeline processor design which exploitssimple hardware structures for register renaming to execute instructionsat a higher rate than known pipeline processors by enabling higher clockfrequency processor designs. In addition, the exemplary embodimentsprovide for a technique to transfer multiple versions of the renamedlogical register data stored in physical registers in one or more renameregister files to another set of architected register files usingsimpler hardware logic to minimize the number of physical registersneeded for renaming. The exemplary embodiments demonstrate a method ofimplementing a register-renaming scheme for a digital data processorusing a plurality of physical register files for supporting out-of-orderexecution of a plurality of instructions.

According to the exemplary embodiments, these features are accomplishedby providing:

(1) A register renaming scheme that uses a number of tables that areaccessed by index in different pipeline stages during execution in lieuof renaming schemes that use associative searches,

(2) Using a DEF table to store the dependencies between instructionsusing instruction tags,

(3) Using a rename USE table indexed by instruction tags to store thelogical-to-physical register mapping information that are shared bynon-architected copies of different types of registers written byinstructions from multiple threads, and

(4) Using a last USE table to efficiently transfer logical register dataresiding in multiple physical register files into an architectedregister file.

Contemporary OO (out-of-order) superscalar processors perform registerrenaming for target registers of all the instructions first, and thenperform out-of-order issue from an issue queue. This is similar to aregister allocation followed by an instruction scheduling scheme in acompiler, and therefore may be subject to similar phase-orderingproblems. It has been shown that combined register allocation andscheduling can generate better quality code. Therefore, it may bepossible to reduce the number of physical registers needed and theassociated renaming (mapper) logic complexity, if the renaming isperformed only when an instruction is selected for issue. Similar to thecombined register allocation and scheduling based code generationschemes, in order to make the best use of the resources, renaming isrequired to be performed, on demand, as late as possible at theinstruction wake-up/issue time. The exemplary embodiments provide ascheme to implement such an efficient out-of-order execution ofinstructions in an OO superscalar processor.

A pipeline of an out-of-order superscalar processor includes of a numberof stages. FIG. 1 illustrates pipeline stages that are relevant to theexemplary embodiments. Instructions are fetched via the fetch block 10from the memory 22 that is closest to the processor (not shown). Thefetched instructions go through a number of front-end pipeline stagesimplementing the functions such as decoding, cracking, grouping, etc.before it reaches the pipeline stage for tracking 12 the instructiondependencies. The instruction dependencies are often tracked based onthe logical register names. In the exemplary embodiments, instructiondependencies are tracked using the instruction tags (or Itags) tosimplify the hardware structures needed for renaming. Specifically, thepipeline stages implementing such functions are a rename block 14, aplurality of issue blocks 24, and a completion block 20.

Every instruction (or an (IOP Internal operation), in case theinstruction is cracked into simple internal operations or substitutedwith a set of internal instructions known as its milli-code) has a setof source operands and destination operands specified using logicalregister names. An instruction writing to a destination logical registeris called its “DEF instruction.” An instruction reading a value from asource logical register is called the “USE instruction” of the sourceregister.

A DEF table is used for tracking the dependencies between instructions.Specifically, it is used for identifying the most recent (youngest)instruction writing to a logical register. The DEF table is indexed bythe logical register name. It has one entry per logical register,consisting of the Itag (lastDEFitag) of the youngest DEF instruction anda valid bit. In a multi-threaded processor, such as a simultaneouslymultithreaded (SMT) processor, there is one DEF table for each registertype per thread.

There are two sets of physical register files called the ArchitectedRegister Files (ARF) 18 and the Rename Register Files (RRF) 16 forstoring the architected and non-architected copies of register values,as shown in FIG. 1. Note that there are a plurality of RRF filesincorporated in the RRF block 16 and a plurality of ARF filesincorporated in the ARF block 18. Typically each type of registers usedby instructions, such as GPRs, FPRs, and VRs, has a separate copy of ARFand RRF. The ARF 18 stores the architected state of the registers, whichis the non-speculative of the logical register values written byinstructions that are committed. A physical register in ARF 18 has afixed one-to-one mapping with logical registers, and hence ARF 18 isindexed by the logical register names. The RRF 16 is used for storingmultiple versions of the logical register values written by instructionsthat are executed speculatively and/or out-of-order. The physicalregisters in RRF 16 are mapped to any logical registers by aregister-renaming unit (mapper). The registers written by instructionsthat are in-flight (dispatched, but not completed) are mapped to RRF 16.The oldest versions of the logical register data in RRF 16 are copied toARF 18 when its DEF instruction is committed. However, an RRF entrycannot be reused (or used as the target for renaming) until all theinstructions in-flight that may use it are also committed.

FIG. 3 illustrates one example of a structure for assigning physicalregisters to logical registers and reclaiming rename registers. A renameUSE table 303 is used for storing the physical-to-logical register namemapping information. The rename USE table 303 is indexed by theinstruction tag (Itag) 304 of the DEF instruction. Therefore, eachinstruction has an entry in the rename USE table 303, and a USE tableentry consists of the tag (Rtag, the index used to access the RRF) ofthe physical register location used for storing the logical registervalue written by the instruction, the type 305 of the register writtenby the instruction and a valid (V) bit. The rename register file for agiven register type is shared by multiple threads in a multi-threadedprocessor.

In the “dependency tracking” stage of the pipeline (after fetch anddecode stages), incoming instructions access the DEF table to read outthe Itag of the DEF instruction for each one of its source operands(logical registers), replace the lastDEFitag entry corresponding to itsdestination logical register with its Itag and set the V bit. The V bitis reset when an instruction is committed or flushed.

Referring to FIGS. 2 and 3, a last USE table 200, 301 is used to keeptrack of the last instruction that reads a given logical register valueresiding in the RRF. The last USE table is indexed by the physicalregister name (Rtag) in RRF. For each physical register in the RRF thereis an entry in the last USE table, which stores the Itag of the youngestinstruction (LastUseItag 201, 302) that reads it, as shown in FIGS. 2and 3.

FIG. 3 illustrates one example of a table showing operations forallocating and freeing physical registers to logical registers. Therenaming (mapping) of a destination logical register is performed byassigning the Rtag (the index used to access the RRF) of a physicalregister to it. The renaming operation is carried out in the “renamestage” of the pipeline as shown as in FIG. 1, which can be as late as inthe issue stage. The rename USE table entry corresponding to the Itag ofthe instruction being renamed is updated by writing the Rtag of the RRFregister assigned to its destination register and setting the V bit. Atthe time of renaming an instruction, the last USE table entrycorresponding to the Rtag assigned to its destination register isupdated by copying the Itag of the instruction to it as its last USEinstruction. There is a free-list generation logic that keeps track ofthe physical registers in RRF that are not mapped to any logicalregisters and an allocation buffer to keep a subset of the Rtags of suchfree physical registers.

The Rtags of the physical registers mapped to the source operand logicalregisters are needed to access the source operand values for executingan instruction. The logical register value can reside in either ARF orRRF. The RRF has a copy of source register value if its DEF instructionis still in-flight or there is at least one in-flight instruction thatmay try to access it; otherwise the source register value can be readfrom the ARF. The Itag of the DEF instruction of the source register isused to read out the Rtag of the physical register assigned to thesource logical register from the rename USE table if V bit is set. Ifthe V bit in rename USE table is zero (reset) then the value can be readfrom the ARF (using the logical register name as the Rtag of the ARF).If a source operand register is found to be mapped to a physicalregister in RRF at the time of renaming an instruction, its mappedphysical register's LastUseItag 302 in the last USE table is replacedwith the Itag 304 of the USE instruction being renamed.

In order to efficiently use the physical registers in RRF, the renamedcopies of the logical register values in the RRF are to be copied to ARFand the mapped physical register in RRF is to be marked free as soon aspossible. This can be performed by using the LastUseItag 302, which isthe Itag of the last in-flight instruction that may read the mappedphysical register in RRF. At the time of completion of an instruction,the destination register value is moved from RRF to ARF. However, the Vbit in the rename USE table cannot be reset to indicate that thephysical register can now be moved to free-list until it is certain thatno in-flight instructions tries to access its copy in RRF. At the timeof committing an instruction, its Itag is compared with the LastUseItag302 (in last USE table) for each of its source operands if it isaccessed from RRF. If the Itags are the same, then it is determined thatthere are no younger instructions in-flight that can access thisphysical register, and hence this rename register can be marked free bysetting the V bit in rename USE table and setting the F bit in the freelist. The V bit is reset and the F bit is set whenever instructions areflushed as well.

Furthermore, the physical registers are partitioned into two sets. Oneset of physical registers has a fixed one-to-one mapping witharchitected registers, henceforth referred to as “architected registerarray/file.” The other set of physical registers, henceforth referred toas “rename register array/file,” is mapped to any architected registersby a register-renaming unit (mapper). The registers used by instructionsthat are in-flight (dispatched, but not completed) are mapped to eitherone or both of the above physical registerfiles. The mapper logicperforms the register renaming by mapping the architected register toone of the physical registers in the rename registerfile. It also keepsa copy of the previous mapping info for flush/recovery. The dispatchunit sends instructions to the appropriate issue queues whenever theissue queue can accept new instructions, usually without renaming thetarget registers (i.e., using registers in the architectedregisterfile). However, if the target register of an instruction isalready renamed and mapped to a physical register in the renameregisterfile, then the target register is renamed prior to dispatchusing the mapper logic.

The wake-up logic identifies all the instructions residing in the issuequeue that are “data ready” and selects one or more of the instructionsto be issued to the appropriate execution pipelines 24. Whenever thereare no data ready instructions in the issue queue and if one or more ofthe instructions in the issue queue can be made data ready by registerrenaming, the target register of such instructions are renamed using themapper logic, provided there are free registers in the rename registerarray.

As a result, the exemplary embodiments provide for a technique forimplementing an area and power efficient renaming scheme for a digitaldata processor using multiple physical register files. The exemplaryembodiments further provide for an improved pipeline processor designwhich exploits simple hardware structures for register renaming toexecute instructions at a higher rate than known pipeline processors byenabling higher clock frequency processor designs. In addition, theexemplary embodiments provide for a technique to transfer multipleversions of the renamed logical register data stored in physicalregisters in one or more register files to another architected registerfile using simpler hardware logic by maximizing the usage of physicalregisters used for rename registers.

The capabilities of the present invention can be implemented insoftware, firmware, hardware or some combination thereof.

As one example, one or more aspects of the present invention can beincluded in an article of manufacture (e.g., one or more computerprogram products) having, for instance, computer usable media. The mediahas embodied therein, for instance, computer readable program code meansfor providing and facilitating the capabilities of the presentinvention. The article of manufacture can be included as a part of acomputer system or sold separately.

Additionally, at least one program storage device readable by a machine,tangibly embodying at least one program of instructions executable bythe machine to perform the capabilities of the present invention can beprovided.

The flow diagrams depicted herein are just examples. There may be manyvariations to these diagrams or the steps (or operations) describedtherein without departing from the spirit of the invention. Forinstance, the steps may be performed in a differing order, or steps maybe added, deleted or modified. All of these variations are considered apart of the claimed invention.

While the preferred embodiment to the invention has been described, itwill be understood that those skilled in the art, both now and in thefuture, may make various improvements and enhancements which fall withinthe scope of the claims which follow. These claims should be construedto maintain the proper protection for the invention first described.

1. A method for implementing a register renaming scheme for a digitaldata processor using a plurality of physical register files forsupporting out-of-order execution of a plurality of instructions, themethod comprising: partitioning the plurality of physical register filesinto a first set of register files having a fixed one-to-one mappingwith a first set of logical registers in the architected state and intoa second set of register files being mapped to a second set havingmultiple copies of logical registers in a non-architected state by aregister-renaming unit; assigning an instruction tag to each of theplurality of instructions for tracking instruction dependencies; using aDEF table to store the instruction dependencies between the plurality ofinstructions using the instruction tags, the DEF table being indexed bya logical register name and including one entry per logical register;using a rename USE table indexed by the instruction tags to storelogical-to-physical register mapping information shared by multiple setsof different types of non-architected copies of logical registers usedby multiple threads; using a last USE table to transfer data of themultiple sets of different types of non-architected copies of logicalregisters into the first set of architected registered files, the lastUSE table being indexed by a physical register name in the second set ofrename registered files; and performing the register renaming scheme atan instruction dispatch or wake-up/issue time in order to reduce anumber of the plurality of physical register files.
 2. The method ofclaim 1, wherein the register-renaming unit is a mapper.
 3. The methodof claim 2, wherein the mapper maps the first set of logical registersto a plurality of physical registers in a rename registerfile andmaintains a copy of previous instruction dependency information for aflush/recovery function.
 4. A system for implementing a registerrenaming scheme for a digital data processor using a plurality ofphysical register files for supporting out-of-order execution of aplurality of instructions, the system comprising: a network; and a hostsystem in communication with the network, the host system includingsoftware to implement a method comprising: partitioning the plurality ofphysical register files into a first set of register files having afixed one-to-one mapping with a first set of logical registers in thearchitected state and into a second set of register files being mappedto a second set having multiple copies of logical registers in anon-architected state by a register-renaming unit; assigning aninstruction tag to each of the plurality of instructions for trackinginstruction dependencies; using a DEF table to store the instructiondependencies between the plurality of instructions using the instructiontags, the DEF table being indexed by a logical register name andincluding one entry per logical register; using a rename USE tableindexed by the instruction tags to store logical-to-physical registermapping information shared by multiple sets of different types ofnon-architected copies of logical registers used by multiple threads;using a last USE table to transfer data of the multiple sets ofdifferent types of non-architected copies of logical registers into thefirst set of architected registered files, the last USE table beingindexed by a physical register name in the second set of renameregistered files; and performing the register renaming scheme at aninstruction dispatch or wake-up/issue time in order to reduce a numberof the plurality of physical register files.
 5. The system of claim 4,wherein the register-renaming unit is a mapper.
 6. The system of claim5, wherein the mapper maps the first set of logical registers to aplurality of physical registers in a rename registerfile and maintains acopy of previous instruction dependency information for a flush/recoveryfunction.
 7. The system of claim 6, wherein the plurality of physicalregisters used by in-flight instructions are mapped to either the firstset of logical registers in architected state or to the second set oflogical registers in a non-architected state.